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ADVANCE INFORMATION
Data Sheet PD 60178A
IR1175
Synchronous Rectifier Driver
Features
n Provides constant and proper gate drive to power MOSFETs regardless of transformer output n Minimizes loss due to power MOSFET body drain diode conduction n Stand alone operation - no ties to primary side n Schmitt trigger input with double pulse suppression allows operation in noisy environments n High current drive capability - 2A n High speed operation - 2MHz n Adaptable to multiple topologies (such as singleended forward, double-ended forward)
Product Summary
Vdd IO+/Fmax Max lead time 5Vdc 2A/2A 2MHz 500nsec
Description
The IR1175 is a high speed CMOS controller designed to drive N-channel power MOSFETs used as synchronous rectifiers in high current, high frequency forward converters with output voltages equal or below 5VDC. Schmitt trigger inputs with double pulse suppression allow the controller to operate in noisy environments. The circuit does not require any ties to the primary side and derives its operating power directly from the secondary. The circuit functions by anticipating transformer output transitions, then turns the power MOSFETs on or off before the transitions of the transformer to minimize body drain diode conduction and reduce associated losses. Turn on/off lead time can be adjusted to accommodate a variety of power MOSFET sizes and circuit conditions. The IR1175 also provides gate drive overlap/dead-time control via external components to further minimize diode conduction by nulling effects of secondary loop and device package inductance.
Package
20 Lead Surface Mount (SSOP-20)
IR1175
ADVANCE INFORMATION
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur.
Symbol
Vdd Iin PD Rth JC RthJA TJ TS TL
Definition
Supply voltage Input clamp current Power dissipation (SSOP-20) Thermal resistance (SSOP-20) junction-to-case Thermal resistance (SSOP-20) junction-to-ambient Junction temperature Storage temperature Lead temperature (soldering, 10 seconds)
Min.
-- -- -- -- -- -- -55 --
Max.
7 +/- 10 400 28.5 90.5 150 150 300
Units
VDC mA DC mW C/W C/W C C C
Recommended Operating Conditions
Symbol
Vdd TA Freq Rbias UV Xin Cd1/Cd2 Cf
Definition
Supply voltage operating range Ambient temperature Operating frequency Required bias resistor (+/- 1%) Voltage at UVSET pin Maximum voltage at X1 and X2 inputs Capacitance at pins DTIN1 and DTIN2 Loop filter bypass capacitor
Min.
-- -40 250 -- 1.75 -- -- 470
Typ.
5 -- -- 69.8 -- -- -- --
Max.
-- 85 500 -- 2.25 5.6 22 --
Units
VDC C KHz KW VDC VDC pF KW
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ADVANCE INFORMATION
IR1175
Dynamic Electrical Characteristics
Vdd=5V, TA = 25 oC, Rbias = 69.8K unless otherwise specified.
Symbol
Vdd Iqdd Freq UVSET+ UVSETVxth+ VxthTadv Td Isink Isource tio tr tf Vtr Rbias Vbias Tjitter Ichgpump Vchgpump Kvco_dc
Definition
Supply voltage operating range Vdd quiescent current (Vin=0 or 5V, Iout=0) Operating frequency UVSET positive going threshold UVSET negative going threshold X1/X2 Input positive going threshold X1/X2 Input negative going threshold Externally adjustable lead time (advance) Externally adjustable dead-time for Q1 and Q2 Q1,Q2 output sink current (Vdd=5.0V, pulsed, 10 usec) Q1,Q2 output source current (Vdd=5.0V, pulsed, 10 usec) Input to output delay (PLL bypassed, cross coupled mode) Gate turn-on rise time (C1=1000pf, Vdd=5V) Gate turn-off fall time (C1=1000pf, Vdd=5V) Cross-over voltage (Vdd=5Vdc, DTIN shorted to DTOUT, C1=1000pf) Fig. 3 Required bias resistor Voltage at Rbias pin Phase-lock loop output jitter Charge pump output current (at VFLTR pin) Charge pump output voltage (at VFLTR pin) PLL Vco DC gain
Min.
4.0 -- 100 1.10 0.8 -- -- -- 20 -- -- -- -- -- -- 68 -- -20 -- 1.3 --
Typ.
-- 3 -- -- -- 1.4 1.0 -- -- -- -- 20 20 20 2.5 -- 1.25 -- 50 1.5 62
Max.
5.5 5 2000 1.4 1.1 -- -- 500 -- 2 2 -- -- -- -- 71 -- 20 -- 1.7 --
Units
VDC mADC KHz V V VDC VDC nsec nsec A A nsec nsec nsec VDC KW VDC nsec mADC VDC KHz/
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IR1175
ADVANCE INFORMATION
Lead Definitions and Assignments
Symbol Description
AVDD Q1 DTIN1 RADV1 VFLTR1 RVCO1 X1 VDD UVSET RBIAS AVSS X2 RVCO2 VFLTR2 RADV2 DTIN2 VSS Q2 Power - + 5 VDC to MOSFET drivers Output - gate drive for Q1 power MOSFET Input - sets dead time for Q1 - used with DTOUT1 Output - sets lead time (advance) for Q1 Output - PLL loop filter for Q1 output Output - sets PLL center frequency for Q1 output Input - transformer input for Q1 Power - +5 Vdc for internal logic Input - sets UVLO+ If this pin is pulled below 1.25VDC externally, then both Q1 and Q2 outputs will be at Vss (disabled) Output - connected to 249K +/- 1% resistor - sets operating current Ground for logic supply (AVDD) Input - transformer input for Q2 Output - sets PLL center frequency for Q2 output Output - PLL loop filter for Q2 Output - sets lead time (advance) for Q2 Input - sets dead time for Q2 - used with DTOUT2 Ground for MOSFET driver supply (VDD) Output - gate drive for Q2 power MOSFET
DTOUT1 Output - sets dead time for Q1 output - used with DTIN1
DTOUT2 Output - sets dead time for Q2 - used with DTIN2
Q2 20
VSS 19
DTOUT1 18
DTIN1 17
RADV2 16
VFLTR2 15
RVCO2 14
X2 13
AVSS 12
RBIAS 11
20 Lead SSOP
IR1175
DTOUT2 VFLTRI RADV1 RVCO1 *VDD UVSET
10
DTIN2
Q1
1
2
3
4
5
6
7
8
9
AVDD
X1
4
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ADVANCE INFORMATION
IR1175
Fig. 1 Typical application circuit when supply Vout < 5.0 VDC
Fig. 2 Typical application circuit when supply Vout = 5.0 VDC www.irf.com 5
IR1175
ADVANCE INFORMATION
Fig. 3 Gate drive characteristics and definitions
Phase Lock Loop Design Equations:
1 - Resistor to set VCO Ceter Frequency: Rvco (KW ) = 143 x [Vchgpump(VDC) / fvco(KHz)] x Kvco _ dc(KHz/mA) W m Example (A): Choose Vchgpump = 1.5V, desired frequency (fvco) = 300KHz Rvco = 143 x [1.5 /300] x 62 Hz/mA = 44.33 KW 2 - Small Signal gain for VCO: Kvco_ac (KHz/Volt) = 1E3 x Kvco_dc (KHz/mA)/(7 x Rvco(KW ) m W Example (B): Choosing same conditions as in example A: Kvco_ac = 1E3 x 62 / (7 x 44.33) = 199.9 KHz/volt
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ADVANCE INFORMATION
IR1175
3 - PLL Natural frequency: n =2fn(KHz)= Ichpump(uA) x Kvco_ac(KHz/V) / C(nF) Choose Cf such that Cf=C/16 (Minimum value for Cf=470pF) 4 - PLL Damping factor calculations: P = E-3 x Rf (KOhms) x C(nF) x fn(KHz) Typical value for P is 0.707. (Critically damped) 5 - Advance timing: Tadv(nsec) = RADV (KOhms)*10 - 10 Where RADV is resistance from RADV1 or RADV2 to ground. Example C: RADV=10Kohms will result in Tadv=10*10 - 10 =90 nsec . 6- Dead time calculations: Td(nsec)=0.69*Rdt(KOhms)*Cdt(pF) + 5 (For Vdd=5 V) Where Rdt is resistance between pins DTIN1 and DTOUT1 or DTIN2 and DTOUT2. Cdt is capacitance from DTIN1 or DTIN2 to ground. Example D: Rdt=10Kohms and Cdt=22pF will result in: Td=156.8 nsec
Fig. 4 PLL loop filter component definitions
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IR1175
ADVANCE INFORMATION
Fig. 5 IR1175 Block Diagram 8 www.irf.com
ADVANCE INFORMATION
IR1175
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020 IR JAPAN: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo, Japan 171-0021 Tel: 8133 983 0086 IR HONG KONG: Unit 308, #F, New East Ocean Centre, No. 9 Science Museum Road, Tsimshatsui East, Kowloon, Hong Kong Tel: (852) 2803-7380 Data and specifications subject to change without notice. 1/27/2000
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